Synchronization in coupled Ikeda delay systems Experimental observations using Field Programmable Gate Arrays

Field Programmable Gate Array–based Implementation of an Improved Algorithm for Objects Distance Measurement (TECHNICAL NOTE)

In this work, the design of a low-cost, field programmable gate array (FPGA)-based digital hardware platform that implements image processing algorithms for real-time distance measurement is presented. Using embedded development kit (EDK) tools from Xilinx, the system is developed on a spartan3 / xc3s400, one of the common and low cost field programmable gate arrays from the Xilinx Spartan fami...

High - Performance Routing for Field - Programmable Gate Arrays

The advantages of field-programmable gate arrays (FPGAs) are sometimes eclipsed by a substantial performance penalty due to signal delay through the programmable routing resources. W e propose Q new FPGA routing construction that directly minimizes source-sink signal propagation delay based on a graph generalization of rectilinear Steiner arborescences (i.e., shortest-paths trees with minimum w...

Secure FPGA Design by Filling Unused Spaces

Nowadays there are different kinds of attacks on Field Programmable Gate Array (FPGA). As FPGAs are used in many different applications, its security becomes an important concern, especially in Internet of Things (IoT) applications. Hardware Trojan Horse (HTH) insertion is one of the major security threats that can be implemented in unused space of the FPGA. This unused space is unavoidable to ...

Phase Synchronization in Unidirectionally Coupled Ikeda Time-delay Systems

Phase synchronization in unidirectionally coupled Ikeda time-delay systems exhibiting non-phase-coherent hyperchaotic attractors of complex topology with highly interwoven trajectories is studied. It is shown that in this set of coupled systems phase synchronization (PS) does exist in a range of the coupling strength which is preceded by a transition regime (approximate PS) and nonsynchronous r...

Delay-based Pattern Recognition Using Field-programmable Gate Arrays